Technology of a depth-2 full-adder circuit using the InP RTD/HFET MOBILE
The technology of resonant tunneling device logic circuits using a modified monostable–bistable transition logic element (MOBILE) is presented. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. The improvements of the basic MOBILE are motivated from the circuit design point of view, and comprise a separate power supply and clock, a dual threshold voltage process, and on-chip clock delay lines. The demonstrator circuit is a pipelined one-bit full adder on InP-substrate. SPICE simulations are carried-out in order to prove the functionality and to evaluate tolerable clock and supply voltage fluctuations in comparison to device parameter feasibility.
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