Pacha, C.; Auer, U.; Burwick, C.; Glösekötter, P.; Brennemann, A.; Prost, Werner; Tegude, Franz-Josef; Goser, K. F.:

Threshold logic circuit design of parallel adders using resonant tunneling devices

In: IEEE transactions on very large scale integration (VLSI) systems : a joint publication of the IEEE Circuits and Systems Society, the IEEE Computer Society, the IEEE Solid-State Circuits Council, Jg. Vol. 8 (2000) ; Heft 5, S. 558 - 572
ISSN: 1063-8210
Zeitschriftenaufsatz / Fach: Elektrotechnik
Abstract:
Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MO-BILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed  of monolithically integrated resonant tunneling diodes and  heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate, Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are  discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined  carry lookahead addition scheme for this logic family is proposed.

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