Pacha, C.; Kessler, O.; Glösekötter, P.; Goser, K. F.; Prost, Werner; Brennemann, A.; Auer, U.; Tegude, Franz-Josef:
Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic
2000
In: Analog integrated circuits and signal processing: an international journal, Jg. Vol. 24 (2000), Heft Heft 1, S. 7 - 25
Artikel/Aufsatz in Zeitschrift / Fach: Elektrotechnik
Titel:
Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic
Autor(in):
Pacha, C.; Kessler, O.; Glösekötter, P.; Goser, K. F.; Prost, Werner im Online-Personal- und -Vorlesungsverzeichnis LSF anzeigen; Brennemann, A.; Auer, U.; Tegude, Franz-Josef im Online-Personal- und -Vorlesungsverzeichnis LSF anzeigen
Erscheinungsjahr
2000
Erschienen in:
Analog integrated circuits and signal processing: an international journal, Jg. Vol. 24 (2000), Heft Heft 1, S. 7 - 25
ISSN
WWW URL

Abstract:

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic Sates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.