A 40 Gb/s optical receiver in 80-nm CMOS for short-distance high-density interconnects
In: 2nd IEEE Asian Solid-State Circuit Conference (A-SSCC 2006) - Session 14-1
Hangzhou, China (2006), S. 395-398
ISBN: 0-7803-97375-5, 0-7803-9734-7
Buchaufsatz / Kapitel / Fach: Elektrotechnik
An optical receiver for short-range optical data communication up to 40 Gb/s is presented. The optimum number of limiting amplifier (LA) stages is calculated to achieve a large gain-band-width product. The receiver features an electrical transimpedance gain of 91.4 dBΩ and a bandwidth of 19.2 GHz. For the free-space optical measurements (λ=1550nm) an InGaAs/InP photo diode (PD) and the CMOS receiver chip were placed and bonded on a test substrate. At 40 Gb/s an open eye at the output of the receiver is shown at an optical input power of -4.6 dBm. Including the transmitter non-idealities, sensitivities at 20 Gb/s and 30 Gb/s of -8.2 dBm and -7.5 dBm, respectively, at a BER = 10e-12 were measured. The complete receiver consumes 56 mW from a 1.1-V supply and occupies a chip area of 230 µm x 220 µm only.
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